In an integrated circuit, an integrated circuit pattern can be formed on a substrate using various fabrication technologies that include photolithography patterning, etching, deposition and ion implantation. Thus formed integrated circuits include various devices, such as field-effect transistor, diode, bipolar transistor, imaging sensor, light-emitting diode, memory cell, resistor, and capacitor, integrated together. A memory device may include a passive device, such as a capacitor or a resistor coupled with other devices, such as a field-effect transistor. In the existing technologies, a passive device, such as a resistor, is formed through various semiconductor technologies that include etching. Those technologies have limited and inaccurate control to dimensions of the passive device, which causes high variations of the device dimensions and the device performance as well. In some cases, the device parameters may run out of the specification and fail the circuit. Furthermore, the existing methods are hard to be implemented in the advanced technology nodes due to high processing variation and small feature sizes. Especially, when the semiconductor technologies move forward to advanced technology nodes with smaller feature sizes, such as 7 nm or less, the misalignments have less tolerance and may cause leakage, short, opening or other failure defects or reliability issue. Therefore, the present disclosure provides a structure and a method making the same to address the above issues.